1. Technical Field
The present invention relates to a semiconductor memory apparatus, and in particular, to an on-die termination circuit and an on-die termination method for a semiconductor memory apparatus.
2. Related Art
In general, when a signal to be transmitted through a bus line having a predetermined impedance meets another bus line having a different impedance, a portion of the signal is lost. Accordingly, an on-die termination (hereinafter, referred to as “ODT”) technique is used to match the impedance of the two bus lines with each other, to thereby reduce the signal loss.
As shown in FIG. 1, an on-die termination circuit according to the related art includes an ODT input driver 10 that is modeled like a data input driver, which divides a power supply voltage VDDQ on the basis of a resistance ratio according to a first code Pcode<0:N>, and outputs a first line voltage P_out, a first ODT controller 20 that compares the first line voltage P_out and a reference voltage Vref and counts the first code Pcode<0:N> according to the comparison result, an ODT output driver 30 that is modeled like a data output driver, that divides the power supply voltage VDDQ on the basis of a resistance ratio according to a second code Ncode<0:N>, and outputs a second line voltage N_out, and a second ODT controller 40 that compares the second line voltage N_out and the reference voltage Vref and counts the second code Ncode<0:N> according to the comparison result.
Upon initial operation, the ODT input driver 10 outputs the first line voltage P_out according to an initial value of the first code Pcode<0:N>.
Next, the first ODT controller 20 compares the first line voltage P_out and the reference voltage Vref and performs an up or down-count of the first code Pcode<0:N> according to the comparison result.
At this time, the ODT input driver 10 receives the counted first code Pcode<0:N> and feeds back the first line voltage P_out according to the counted first code Pcode<0:N> to the first ODT controller 20. Then, the comparison operation of the first ODT controller 20 and the output operation of the first line voltage P_out of the ODT input driver 10 are repeated.
If the first line voltage P_out and the reference voltage Vref are consistent with each other, the first code Pcode<0:N> count operation of the first ODT controller 20 stops, and the ODT operation is completed.
The operations of the ODT output driver 30 and the second ODT controller 40 are the same as those of the ODT input driver 10 and the first ODT controller 20, and thus the descriptions thereof will be omitted.
In the above-described related art, upon adjustment of the first code Pcode<0:N> and the second code Ncode<0:N>, when the first line voltage P_out and the second line voltage N_out are larger than the reference voltage Vref, the resistance values need to be increased. To this end, the value of the first code Pcode<0:N> is increased and the value of the second code Ncode<0:N> is decreased.
At this time, when the impedance of the outside of the memory, that is, the impedance on input/output terminals of the semiconductor memory apparatus is very high, and the line voltage is continuously higher than the reference voltage, the value of the first code Pcode<0:N> is continuously increased and finally becomes a maximum, and thus the resistance value substantially approaches an infinite value. Similarly, the second code Ncode<0:N> is continuously decreased and finally becomes a minimum, and thus the resistance value substantially approaches an infinite value.
Accordingly, in the on-die termination circuit for a semiconductor memory apparatus according to the related art, code adjustment errors, that is, the maximum first code Pcode<0:N> and the minimum second code Ncode<0:N>, occur due to external impedance. Accordingly, the resistance values approach infinite values, and accurate data input/output is not performed.